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使用VHDL语言实现DES数据加密算法

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package des_lib is
component des
port (clk :in std_logic;
reset :in std_logic;
encrypt :in std_logic;
key_in :in std_logic_vector (55 downto 0);
din :in std_logic_vector (63 downto 0);
din_valid :in std_logic;
busy :buffer std_logic;
dout :out std_logic_vector (63 downto 0);
dout_valid :out std_logic
);
end component;
component des_round
port (clk :in std_logic;
reset :in std_logic;
stall :in std_logic;
encrypt_in :in std_logic;
encrypt_shift :in std_logic_vector (4 downto 0);
decrypt_shift :in s