摘要：作为新的和成功的串行数据标准，从快非常快，设计师必须投入较多的时间，这些高速信号的模拟方面。它不再是足够保持在1和0的数字域。发现并纠正导致潜在的问题的条件，从而防止这些问题出现在现场，设计师还必须检查其设计参数的境界。信号完整性（SI ）工程师必须减轻或消除对系统性能的时序抖动的影响。下面的讨论提供了一个简单实用的程序，表征高速串行数据链路1Gbps和以后。

Maxim > Design support > App notes > Basestations/Wireless Infrastructure > APP 4613
Maxim > Design support > App notes > Communications Circuits > APP 4613
Maxim > Design support > App notes > High-Speed Interconnect > APP 4613

Keywords: jitter, clock jitter, data jitter, high-speed serial, signal integrity, SERDES, serializer-deserializer, clock and data recovery,
CDR, jitter tolerance, CPRI, common public radio interface, bit error rate, BER, deterministic jitter, random jitter
Mar 03, 2010
APPLICATION NOTE4613
A Proposed Framework for Measuring, Identifying, and Eliminating
Clock and Data Jitter on High-Speed Serial Communication Links
By:Hamed Sanogo, Field A